The present invention relates to a technique for use in the manufacture of a semiconductor device, particularly, to an effective technique that is suitable for the manufacture of a semiconductor device using block molding by transfer molding.
In the manufacture of a semiconductor device, a method is known in which a plurality of semiconductor chips mounted on a main surface of a substrate are block-molded with one resin enclosure, and then the resin enclosure and the substrate are simultaneously separated into respective semiconductor chips. This manufacturing method is disclosed in Japanese patent Laid-Open No. 107161/1996 (U.S. Pat. No. 5,729,437) (publicly known document 1) and Japanese patent Laid-Open No. 12578/2000 (U.S. Pat. No. 6,200,121) (publicly known document 2), for example. More particularly, the publicly known document 1 discloses a method of forming a resin enclosure for block molding by potting, and the publicly known document 2 discloses a method of forming a resin enclosure for block molding by transfer molding.
The inventors have studied the method for forming a resin enclosure for block molding by transfer molding (hereafter called block transfer molding). Consequently, they have found the following problems.
FIGS. 23A to 26B are diagrams illustrating resin flows when a resin enclosure is formed by block transfer molding in traditional semiconductor device manufacture. In FIGS. 23A to 26B, 60 denotes a substrate, 60X denotes a main surface of the substrate 60, 61 denotes a semiconductor chip, 62 denotes a molding die, 62A denotes an upper mold of the molding die 62, 62B denotes a bottom mold of the molding die 62, 63 denotes a cavity, 64 denotes a gate, 65 denotes a runner, 66 denotes an air vent, 67A denotes a resin, 67B denotes a void and S denotes a resin injecting direction.
Block transfer molding is adopted in the manufacture of a BGA (Ball Grid Array) semiconductor device and a CSP (Chip Size Package or Chip Scale Package) semiconductor device having a package structure with a substrate. In the manufacture of these types of semiconductor devices, the substrate 60, where a plurality of product forming areas 60A are arranged on the main surface 60X in matrix form with a predetermined spacing, is used, as shown in FIG. 23A. Therefore, a plurality of semiconductor chips 61 mounted on the substrate 60 are also arranged in matrix form with a predetermined spacing.
In block transfer molding, the molding die 62, having a cavity 63, gates 64, runners 65, a cull (not shown), pots (not shown) and air vents 66, is used as shown in the drawing. The resin 67A is injected inside the cavity 63 from the pots through the culls, the runners 65 and the gates 64.
Since a substrate 60 having a rectangular plane is generally used, the plane shape of the cavity 63 is also formed into a corresponding rectangular shape. In such case, a plurality of gates 64 are disposed along one of the two long sides of the cavity 63 so that the resin 67A will evenly fill the inside of the entire cavity 63. Thus, the resin 67A is injected inside the cavity 63 from one long side to the other long side of the substrate 60. The resin 67A thus injected inside the cavity 63 flows from one long side to the other long side of the substrate 60 as shown progressively in FIGS. 23A to 25B, and eventually fills the inside the cavity 63, as shown in FIGS. 26A and 26B.
Meanwhile, the resin 67A that has been injected inside the cavity 63 flows along a main surface and the side surfaces of each semiconductor chip 61. The resin 67A flowing along the main surface and the side surfaces of a semiconductor chip 61 runs between the semiconductor chips 61. However, the flow of the resin 67A along the main surface of the semiconductor chip 61 is resisted by the semiconductor chip 61. Therefore, it runs slower than the resin 67A flowing along the side surfaces of the semiconductor chip 61 (see FIGS. 24A and 24B). For this reason, voids 67B tend to be generated at positions where the resin 67A flowing along the main surface of the semiconductor chip 61 meets the resin 67A flowing along the side surfaces of the semiconductor chip 61 (see FIGS. 25A and 25B). The voids 67B gradually become smaller as they are moved by the flow of the resin 67A in the resin injecting process. However, voids 67C remain at positions hiding behind the semiconductor chips 61 with respect to the injecting direction S of the resin 67A (see FIGS. 26A and 26B).
In transfer molding, there is a process for reducing voids that have been caught in the resin by applying a higher injection pressure after resin filling is complete. However, the voids 67C are considerably greater than voids of the type that do not cause the popcorn phenomenon during temperature cycle testing, even though this process is applied. Thus, they become a factor that reduces the yields of semiconductor devices.
The aforementioned publicly known document 1 (Japanese patent Laid-Open No. 107161/1996) discloses the use of a molding material having a low thixotropic property, and further employs vacuum defoaming as a means of preventing the generation of unfilled portions. However, in transfer molding, application of the aforesaid technique cannot solve the problem of void generation.
When transfer molding is adopted, the resin flow is to be controlled by injection from the gates. Therefore, air vents are disposed at positions facing the gates and in areas where the resin is finally filled, and, thereby, air inside the cavity can be removed from the air vents until the resin is filled inside the cavity. However, in transfer molding, when the thixotropic property is reduced to the extent that the resin flow is governed by the thixotropic property, or the resin injecting rate is decreased, it becomes difficult to control the resin flow, and it becomes substantially impossible to set the positions of the air vents that have to be disposed in areas where the resin is finally filled. Accordingly, in transfer molding, it is virtually impossible to control the conditions of the resin in the injecting process and to eliminate generation of voids by adopting a material having a low thixotropic property as the resin.
Additionally, when a great amount of a filler (80% or more, for example) is added to a molding resin for the purpose of reducing warpage due to the cure shrinkage of the molding resin to facilitate the dicing process, or for the purpose of providing a thermal expansion coefficient of the resin closer to that of a semiconductor chip to reduce the stress applied to the semiconductor chip during heat cycling, the existence of the filler increases the thixotropic property even though those resins having a low thixotropic property are adopted as a molding material. Therefore, a low thixotropic property is insufficient as a means of solving the void catching problem.
Furthermore, in potting, a method, such as vacuum defoaming, can be adopted in which air bubbles are removed outside a resin by placing semiconductor devices, that are in a state in which the resin has not been cured, in a low-pressure atmosphere after potting. However, in transfer molding, resin injection and curing are performed inside the cavity, and thus the method for reducing voids by vacuum defoaming cannot be adopted. Consequently, in transfer molding, applying techniques described in the publicly known document 1 cannot prevent the problem of void generation. Therefore, new methods need to be adopted for preventing voids.
Accordingly, the inventors have turned their attention to the wettability of the resin 67A to the main surface of the substrate 60 to develop a technique to prevent the generation of voids 67C which remain on the main surface of the substrate 60, as shown in FIGS. 26A and 26B.
The object of the present invention is to provide techniques capable of improving the yield of semiconductor devices.
The aforementioned object, other objects and new features of the invention will be apparent from the following description and the accompanying drawings.
Among the aspects of invention disclosed in the present application, the following is the brief description of a summary of representative features.
(1) A method of manufacturing a semiconductor device comprises forming a resin enclosure for block-molding of a plurality of semiconductor chips by placing a plurality of semiconductor chips inside a cavity of a molding die along with a substrate and then injecting a resin inside the cavity from a first side to a second side along a main surface of the substrate, the plurality of semiconductor chips being mounted on the main surface of the substrate in an arrangement from the first side to the second side of the main surface with a predetermined spacing, the second side facing the first side, wherein the method further comprises removing impurities remaining on the main surface of the substrate before forming the resin enclosure. Removing impurities remaining on the main surface of the substrate is performed by plasma cleaning.
(2) A method of manufacturing a semiconductor device comprises forming a resin enclosure for block-molding of a plurality of semiconductor chips by placing a plurality of semiconductor chips inside a cavity of a molding die along with a substrate and then injecting a resin inside the cavity from a first side to a second side along a main surface of the substrate, the plurality of semiconductor chips being mounted on the main surface of the substrate in an arrangement from the first side to the second side with a predetermined spacing, the second side facing the first side, wherein the method further comprises the application of surface roughening treatment to the main surface of the substrate before forming the resin enclosure. The surface roughening treatment is performed by plasma cleaning.